1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to various methods of forming strained epitaxially grown semiconductor material(s) above a strain-relaxed buffer (SRB) layer.
2. Description of the Related Art
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. As it relates to both planar and 3D devices (such as FinFETs), device designers have spent many years and employed a variety of techniques in an effort to improve the performance capability and reliability of such devices. Device designers are currently investigating using alternative semiconductor materials, e.g., silicon germanium (SiGe), such as so-called III-V materials, etc., in transistor devices to enhance the performance capabilities of such devices. Devices with high charge carrier mobility with silicon, silicon-germanium or germanium channel materials can be fabricated above a strain-relaxed SiGe layer as a “virtual substrate.” Ideally, such a virtual substrate needs to have a very smooth surface with a low threading dislocation density (TDD). However, the formation of such a virtual substrate comprised of such alternative materials on silicon substrates (the predominate substrates used in the industry) is a non-trivial matter due to, among other issues, the large difference in lattice constants between such alternative channel materials and silicon.
One prior art technique for forming virtual substrates involves performing an epitaxial growth process to form a relatively thick layer of a semiconductor material (“epitaxial semiconductor material layer”), in either a homogenous or graded condition, above a semiconductor substrate, such as silicon. An epitaxial semiconductor material layer that is formed to a thickness greater than a critical thickness for such a semiconductor material relaxes via the introduction of dislocations into the epitaxial semiconductor material layer. This critical thickness of the epitaxial semiconductor material layer is mainly determined by compositional differences between the epitaxial semiconductor material layer and the substrate, the growth conditions (growth rate, temperature, etc.) and by the defects present in the epitaxial semiconductor material layer and/or at the heterointerface between the epitaxial semiconductor material layer and the underlying substrate. Although reduced threading dislocation densities can be obtained by this method, thick buffer layers still present some major drawbacks, e.g., growth time, material consumption, thermal budget and so on, while typically not achieving required TDD levels.
With respect to forming such lattice-constant-mismatched materials on one another, there is a concept that is generally referred to as the “critical thickness” of a material. Critical thickness is defined as the maximum stable thickness of a completely strained heterostructure material substantially without any misfit dislocations and threading dislocations, which will be described more fully below. FIG. 1A is a graph taken from an article entitled “Silicon-Germanium Strained Layer Materials in Microelectronics” by Douglas J. Paul that was published in Advanced Materials magazine (11(3), 191-204 (1999)). The vertical axis is the critical thickness in nanometers. The horizontal axis is the composition of germanium in the silicon-germanium material (Si1-xGex; x=0-1). At the leftmost point on the horizontal axis is pure silicon (Ge composition equals 0.0). At the rightmost point on the horizontal axis is pure germanium (Ge composition equals 1.0). The two curves R and S define the stable, metastable and relaxed-with-defects regions for silicon-germanium materials having differing germanium composition levels. Above and to the right of curve R are materials that are in the relaxed-with-defects condition. Below and to the left of curve S are materials that are in the stable condition (i.e., substantially defect-free and in a “fully-strained” condition). The region between the two curves R and S defines the region where materials are in the metastable condition. A material in the metastable condition is not stable, but can still be fully strained and substantially defect-free if grown under the right conditions. However, this metastable material could relax (with the associated defects being formed) relatively quickly when the environment is changed, e.g., when the metastable material is annealed.
With reference to FIG. 1A, a layer of pure germanium (Ge composition equal to 1.0) may be in the stable condition at a thickness up to about 1-2 nm (point CT1) and it may be in a metastable condition for thicknesses between about 2-4 nm (point CT2). Above a thickness of about 4 nm, a layer of pure germanium will be in the relaxed-with-defects condition. In contrast, a layer of silicon-germanium with 50% germanium may be in the stable condition at thicknesses up to about 4 nm (point CT3) and it may be in a metastable condition for thicknesses between about 4-30 nm (point CT4). Above a thickness of about 30 nm, a layer of silicon-germanium with a 50% composition of germanium will be in the relaxed-with-defects condition.
As to dislocations in such SiGe materials, there are at least two types of dislocations worth mentioning—misfit dislocations and threading dislocations. In general, a misfit dislocation occurs where this is a missing or extra lattice between two layers with different lattice constants. In Si/SiGe heterostructures, when SiGe is grown above its critical thickness, misfit dislocations occur due to the mismatch between the lattice constant of the grown material and the silicon substrate. These misfit dislocations will typically be oriented at about 60 degrees when SiGe is grown on a (100) silicon substrate. For each misfit dislocation, there will typically be two threading dislocations, each of which initiates at an end of the misfit dislocation. These threading dislocations move or “thread” their way to the surface of the SiGe material, where they effectively terminate. In other cases, the misfit dislocations can also terminate at an edge of a semiconductor wafer or at other suitable boundaries without the formation of threading dislocations.
FIGS. 1B-1E depict one illustrative prior art technique where alternative channel materials will be formed above the SRB structure. FIG. 1B depicts a device 10 wherein a first silicon germanium layer 14, with a composition of, for example, Si0.75Ge0.25, is grown on the surface of a silicon substrate 12. The first SiGe layer 14 is grown to a thickness that is greater than its critical thickness. Thereafter a silicon cap layer 16 is deposited on the first SiGe layer 14. The thickness of the silicon cap layer 16 is typically relatively thin, e.g., about 10-20% of the thickness of the first SiGe layer 14, so as to not restrict the relaxation of the SiGe layer 14. FIG. 1C depicts the device 10 after an ion implantation process 18 is performed to implant ions, such as argon. The purpose of implanting the ions is to generate relatively “weak points” in the substrate 12 for nucleation of dislocations later in the process flow, i.e., so that formation of misfit dislocations and threading dislocations in the first SiGe layer 14 may be easier to generate. FIG. 1D depicts the device 10 after an anneal process (e.g., 750-1050° C.) is performed that results in the formation of misfit dislocations at the interface between the substrate 12 and the first SiGe layer 14 (dislocation not shown) and simplistically depicted threading dislocations 26 that extend through the first SiGe layer 14. Some of the threading dislocations in the first SiGe layer 14 will also annihilate with dislocations of opposite sign. Those threading dislocations that are not annihilated would ideally terminate at the upper interface with the silicon cap 16. In other words, ideally all of the threading dislocations 26 will be trapped in the first SiGe layer 14 and not penetrate into the silicon cap layer 16. At this point in the process, the first SiGe layer 14, which was originally strained when formed, is now relaxed with dislocations, while the silicon cap layer 16 is in a tensile strained condition with the same lateral lattice parameter of the now-relaxed first SiGe layer 14. FIG. 1E depicts the device 10 after a second silicon germanium layer of material 28 was formed on the silicon cap layer 16. In theory, since the first SiGe layer 14 is now relaxed, substantially all of the threading dislocations 26 were trapped under or at the interface with the silicon cap layer 16, and the silicon cap layer 16 itself is substantially free of threading dislocations, the second SiGe layer 28 may be grown to any desired thickness in a substantially dislocation-free condition if it has the same germanium composition as the first silicon germanium layer 14, e.g., Si0.75Ge0.25. Thereafter, although not depicted in the drawings, additional epitaxial semiconductor material (Si for N-type devices and SiGe0.5 for P-type devices) may be grown on the second SiGe layer 28 using appropriate masking strategies if needed.
While the above-described process has been somewhat successful in producing SRB structures with low TDD values, the quality of such SRB structures is still not sufficient to provide virtual substrates for future generation transistor devices. Ideally, the SRB structure would be formed with zero threading dislocations, but, as a practical matter, there will always be some threading dislocations present in the SRB structure. As it relates to the formation of such SRB structures for future device generations, a target goal would be to achieve a TDD of nearly zero. The above-described process flow (FIGS. 1B-1E) typically results in a TDD of about 1×104 dislocations/cm2.
It is believed that the above-described process flow for forming the SRB structure is not as effective as would otherwise be desired for several reasons. First, during the ion implantation process 18 (FIG. 1C), the distribution of the implanted ions does not result in a very small vertical distribution of ions centered at the interface 20 between the substrate 12 and the first SiGe layer 14. Rather, due to straggle in the ion implantation process 18, some of the implanted ions are vertically distributed throughout the thickness of the first SiGe layer 14, some may be positioned at the silicon cap layer 16, and some may be positioned in the silicon substrate 12. As a result, the threading dislocations may originate and propagate into or through the silicon cap layer 16. If so, such dislocations will also propagate into the second SiGe layer 28 when it is formed. Second, in some cases, the silicon cap layer 16 is simply not effective in trapping all of the dislocations as some of the dislocations propagate to the surface of the silicon cap layer 16. Such a situation may arise when an aggressive anneal process 24 is performed to cause the formation of the threading dislocations 26. FIG. 1F is a TEM photograph depicting the propagation of dislocations through the silicon cap layer 16 and into the second silicon germanium layer of SiGe material.
The present disclosure is directed to various methods of forming strained epitaxially grown semiconductor material(s) above a strain-relaxed buffer (SRB) layer that solves or reduces one or more of the problems identified above.